1. Technical Field
The present disclosure relates to on-chip inductor performance and, more specifically, to a package integrated soft magnetic film for improvement in on-chip inductor performance.
2. Discussion of the Related Art
Large groups of integrated circuits (ICs) are generally produced on a single semiconductor wafer. The wafer is then cut into small units called dies with each die containing the integrated circuit. Each die is then contained into a small package that protects the die and facilitates interconnection. The package may be made of an insulating material such as ceramic, plastic, or epoxy. The package may also include a grounded plane made of a conductive material such as a metal.
The integrated circuits may contain a variety of miniaturized electrical devices and interconnections. One such electrical device is the inductor. The inductor is a circuit element that opposes change in current with an inductance L. The inductor may be especially useful in analog circuits and mixed-signal circuits. The inductor may foe formed by a conductive coil. An ideal inductor has no resistance. However, typical inductors have a resistance R that results from resistive losses in the conductive coil. The resistance of the inductor may convert current flowing through the coil into heat, thus causing a loss of inductive quality. Typically, the inductive quality may be expressed in terms of an inductor Q-factor where the Q-factor represents a frequency-dependent ratio of inductance, L, over coil resistance, R. Accordingly, the Q-factor represents a measure of an inductor's efficiency. The higher the Q-factor of the inductor, the closer the inductor is to behaving like an ideal, lossless inductor.
Miniaturized inductors that are formed within the IC are referred to as on-chip inductors. On-chip inductors may be formed as a conductive spiral using conventional IC processing techniques and are typically of planar nature. On-chip inductors are generally formed using the topmost metal layers of an IC process as these top metal layers tend to foe thicker and have lower resistances than other layers of the IC. Moreover, forming on-chip inductors on the top metal layers is commonly employed to reduce capacitive coupling to the conductive substrate below.
While there are many methods available for mounting IC chips for use, the flip-over die or flip chip is mounted without the need for wire bonds. Here, solder bumps are deposited on the chip pads. The IC is then mounted upside down in the package and the solder is reflowed. This mounting is also known as controlled collapse chip connection (C4).
For flip-over die, the top metal layer of the IC chip which includes the miniaturized inductors will be in close proximity to the package lid. This is also the case for a wire bond package or surface of a printed circuit board that the IC is mounted to in a C4 package. Accordingly, the magnetic field of the inductors will couple to the metal connections, or traces, in the package printed circuit board which will negatively affect the inductor performance. For example, the inductance Q-factor may be decreased due to the eddy current set up in the metal connections on the printed circuit board.
One approach to remedy this problem is to re-rout the conductive metal traces in the printed circuit board around areas in close proximity to the on-chip inductors. Alternatively or additionally, a large distance may be left between the on-chip inductors and the printed circuit board of the packaging. However, such approaches may be difficult to implement for complex ICs and may reduce the extent to which the circuits may be miniaturized.
Another approach is to incorporate a magnetic material into the IC chip stack both above and below the metal layers used to define the planar inductor. This approach requires complex and expensive alteration and/or post-processing of the IC.